I am a software craftsman, leading the Ksplice engineering team at Oracle, providing rebootless kernel updates for Linux systems. Prior to that I worked at Picochip (later acquired by Intel), where I was responsible for the Linux port for picoxcell devices and embedded security amongst other things. I'm based in Bristol in the UK.
I created the Oldland CPU from scratch, a full-featured 32-bit RISC CPU, written in Verilog and syntheziable on FPGAs. The CPU features a 5 stage pipeline, privilege modes, caches, TLB's and a debug controller. The SoC has an SDRAM controller, SPI master, UART, timers, interrupt controller and other peripherals. I have also ported binutils, gcc, newlib, u-boot and RTEMS to the Oldland architecture.
My current project is a microcoded, 80186 compatible IP core which currently runs at 60MHz on a Cyclone V FPGA in ~1750 ALMs, implementing the full 80186 ISA, traps, faults + interrupts along with a JTAG TAP. The core has a comprehensive test suite using Verilator + Google Test, a C++ model to verify against, and a build system using CMake+Docker.
I have a number of github repositories including the Oldland CPU, the picoxcell Linux kernel tree, some configuration files and a bunch of miscellaneous scripts and projects in progress. My Ohloh profile lists some of my open source contributions, and my CV lists my professional achievements. I've contributed patches to the Linux kernel to add support for ARM performance counters, the picoxcell family of ARM devices and associated drivers, support for device tree on ARM, and other bug fixes and driver improvements.
email: jamie <at> jamieiles <dot> com
gpg: public key, fingerprint:
C622 D8F8 26C1 A1F7 94F5 C53F C686 AD0A 9B42 49F5