I am a software craftsman from the UK, leading the Ksplice engineering team at Oracle which provides rebootless OS updates for Linux systems. I have a keen interest in CPU architecture and all things low-level. I have designed two CPU’s - one x86 compatible and another home-grown 32-bit RISC, both with SoC reference designs.
I have created an 80186 compatible IP core from scratch which currently runs at 60MHz on a Cyclone V FPGA in ~1750 ALMs, implementing the full 80186 ISA, traps, faults + interrupts along with a JTAG TAP. The core has a comprehensive test suite using Verilator + Google Test, a C++ model to verify against, and a build system using CMake+Docker. A reference design includes an SDRAM controller, MCGA graphics, PS/2 keyboard+mouse controller, fixed disk emulation on an SD card, lightweight PIC+PIT implementations and a BIOS. The system can run a wide range of DOS based applications with good performance.
The Oldland CPU is my first home-grown CPU, a full-featured 32-bit RISC CPU, written in Verilog and syntheziable on FPGAs. The CPU features a 5 stage pipeline, privilege modes, caches, TLB’s and a debug controller. The SoC has an SDRAM controller, SPI master, UART, timers, interrupt controller and other peripherals. I have also ported binutils, gcc, newlib, u-boot and RTEMS to the Oldland architecture.
I have a number of github repositories including the s80x86 CPU, Oldland CPU, the picoxcell Linux kernel tree, some configuration files and a bunch of miscellaneous scripts and projects in progress. My Ohloh profile lists some of my open source contributions, and my CV lists my professional achievements. I’ve contributed patches to the Linux kernel to add support for ARM performance counters, the picoxcell family of ARM devices and associated drivers, support for device tree on ARM, and other bug fixes and driver improvements.
Take a look at my resume for professional experience.
email: jamie <at> jamieiles <dot> com
gpg: public key, fingerprint: C622 D8F8 26C1 A1F7 94F5 C53F C686 AD0A 9B42 49F5