Oldland Soft CPU

Oldland is a 32-bit RISC CPU targeted at FPGAs. This is a completely custom architecture, and I implemented the RTL, ported the GNU toolchain, U-Boot and RTEMS to the new architecture. The main features are:

  • 5 stage load/store pipeline.
  • 16 general purpose registers.
  • N-way set-associative blocking instruction/data caches
  • Software managed instruction/data TLBs with 4KB page size.
  • JTAG debug controller for execution control and state modification/inspection.
  • Exception table for interrupts, data/instruction aborts, illegal instruction and software interrupts along with separate ITLB/DTLB miss handlers.
  • User and supervisor modes.
Oldland CPU Core
Keynsham System-on-chip
Keynsham is a SoC using Oldland as the core and has a number of peripherals:
  • 32/64MB SDR SDRAM controller.
  • SPI master with configurable number of chip selects.
  • On-chip bootrom.
  • On-chip memory.
  • Programmable timers.
  • Interrupt controller.
  • UART.
  • SPI master.

There is a C model along with Icarus and Verilator RTL simulations. The Keynsham SoC can be synthesized to run on a Terasic DE0 Nano or DE0-CV. There are ports of binutils, gcc, newlib, u-boot and RTEMS available.

The Terasic DE0-CV using an Altera Cyclone V and the DE0-nano board using an Altera Cyclone IV are the supported boards running at ~75MHz on slow silicon @85°C.