The Keynsham SoC featuring the Oldland CPU now runs on the DE0-CV. The DE0-CV is a bigger board than the DE0-NANO that I was previously using and has a number of nice features:

• A bigger, Cyclone V device.
• 64MB SDRAM versus 32MB on the DE0-NANO.
• VGA output with a simple 12-bit ADC.
• PS/2 controller.
• 6x7 segment displays
• More accessible pushbuttons.

On the new board the Keynsham SoC only uses ~25% of logic resources so there is plenty of room for expansion!

Porting to the new board was a relatively pain-free exercise. To do this, I first added support for multiple SoC configurations, so it is now possible to have a YAML file to describe the memory map of the SoC and some CPU parameters such as cache sizes, number of TLB entries etc.

Editing the pin assignments is a fairly tedious process, as was refreshing the Altera IP components. I couldn’t find an easy way to take a component that was previously instantiated for Cyclone IV and move the same configuration to a Cyclone V so they just had to be manually recreated.

The PLLs on Cyclone V are different and have a couple of extra non-optional ports compared to the Cyclone IV PLLs. In particular, there is a “locked” output and a “reset” input because seemlingly the PLL can lose lock at some point during running. For now I have wired the active high reset to 0 and left the locked output unconnected, but may wire this output to the SDRAM state machine to wait for PLL lock before initialising if this proves important. It doesn’t look like there is a good way to handle the PLL losing lock during running, so that might be a fatal error.

The virtual JTAG and oldland-test script really paid off here - it was very quick to verify that everything was performing as expected. I plan on adding support for the 7-segment display next followed by a text mode VGA controller to take advantage of the DE0-CV features.